CASPT, CASPAT, CASPALT, CASPLT

Compare and swap pair unprivileged

This instruction reads a pair of 64-bit doublewords from memory, and compares them against the values held in the first pair of registers. If the comparison is equal, the values in the second pair of registers are written to memory. If the comparison is not equal, the architecture permits writing the value read from the location to memory. If the writes are performed, the reads and writes occur atomically such that no other modification of the memory location can take place between the reads and writes.

• CASPAT and CASPALT load from memory with acquire semantics.
• CASPLT and CASPALT store to memory with release semantics.
• CASPT has neither acquire nor release semantics.

The architecture permits that the data read clears any exclusive monitors associated with that location, even if the compare subsequently fails.

If the instruction generates a synchronous Data Abort, the registers which are compared and loaded, that is <Xs> and <X(s+1)>, are restored to the values held in the registers before the instruction was executed.

Explicit Memory effects produced by the instruction behave as if the instruction was executed at EL0 if the Effective value of PSTATE.UAO is 0 and either:

• The instruction is executed at EL1.
• The instruction is executed at EL2 when the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}.

Otherwise, the Explicit Memory effects operate with the restrictions determined by the Exception level at which the instruction is executed.

For a CASPT or CASPAT instruction, when <Ws> or <Xs> specifies the same register as <Wt> or <Xt>, this signals to the memory system that an additional subsequent CASPT, CASPAT, CASPALT, or CASPLT access to the specified location is likely to occur in the near future. The memory system can respond by taking actions that are expected to enable the subsequent CASPT, CASPAT, CASPALT, or CASPLT access to succeed when it does occur.

A code sequence starting with a CASPT or CASPAT instruction for which <Ws> or <Xs> specifies the same register as <Wt> or <Xt>, and ending with a subsequent CASPT, CASPAT, CASPALT, or CASPLT to the same location, exhibits the following properties for best performance when the location may be accessed concurrently, on one or more other PEs:

• The sequence does not contain any direct system register writes, address translation instructions, cache or TLB maintenance operations, exception producing instructions, exception returns, or ISB barriers.
• The execution of the sequence includes 32 or fewer instructions.
• The value provided in <Ws> or <Xs> of the first CASPT or CASPAT is a value likely to result in the comparison failing. A failing comparison result may lead to better performance due to the hardware not performing a write to memory.

For more information about memory ordering semantics, see Load-Acquire, Store-Release.

For information about addressing modes, see Load/Store addressing modes.

No offset
(FEAT_LSUI)

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_LSUI) then EndOfDecode(Decode_UNDEF); if Rs<0> == '1' || Rt<0> == '1' then EndOfDecode(Decode_UNDEF); constant integer s = UInt(Rs); constant integer t = UInt(Rt); constant integer n = UInt(Rn); constant integer datasize = 64; constant boolean acquire = L == '1'; constant boolean release = o0 == '1'; constant boolean tagchecked = n != 31;