STFMAX, STFMAXL

Floating-point atomic maximum in memory, without return

This instruction atomically loads a 16-bit, 32-bit, or 64-bit value from memory, computes the floating-point maximum with the value held in a register, and stores the result back to memory.

This instruction:

For more information about memory ordering semantics, see Load-Acquire, Store-Release.

For information about addressing modes, see Load/Store addressing modes.

Floating-point
(FEAT_LSFE)

313029282726252423222120191817161514131211109876543210
size1111000R1Rs110000Rn11111
VRAo3opcRt

Encoding for the Half-precision no memory ordering variant

Applies when (size == 01 && R == 0)

STFMAX <Hs>, [<Xn|SP>]

Encoding for the Half-precision release variant

Applies when (size == 01 && R == 1)

STFMAXL <Hs>, [<Xn|SP>]

Encoding for the Single-precision no memory ordering variant

Applies when (size == 10 && R == 0)

STFMAX <Ss>, [<Xn|SP>]

Encoding for the Single-precision release variant

Applies when (size == 10 && R == 1)

STFMAXL <Ss>, [<Xn|SP>]

Encoding for the Double-precision no memory ordering variant

Applies when (size == 11 && R == 0)

STFMAX <Ds>, [<Xn|SP>]

Encoding for the Double-precision release variant

Applies when (size == 11 && R == 1)

STFMAXL <Ds>, [<Xn|SP>]

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_LSFE) then EndOfDecode(Decode_UNDEF); constant integer s = UInt(Rs); constant integer n = UInt(Rn); constant integer datasize = 8 << UInt(size); constant boolean acquire = FALSE; constant boolean release = R == '1'; constant boolean tagchecked = n != 31;

Assembler Symbols

<Hs>

Is the 16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Ss>

Is the 32-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

<Ds>

Is the 64-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

Operation

CheckFPEnabled64(); bits(64) address; bits(datasize) value; bits(datasize) data; constant AccessDescriptor accdesc = CreateAccDescFPAtomicOp(MemAtomicOp_FPMAX, acquire, release, tagchecked); value = V[s, datasize]; if n == 31 then CheckSPAlignment(); address = SP[64]; else address = X[n, 64]; constant bits(datasize) comparevalue = bits(datasize) UNKNOWN; // Irrelevant when not executing CAS data = MemAtomic(address, comparevalue, value, accdesc);


Internal version only: aarchmrs v2024-12_rel, pseudocode v2024-12_rel ; Build timestamp: 2024-12-15T22:18

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