Load register signed word (literal)
This instruction calculates an address from the PC value and an immediate offset, loads a word from memory, and writes it to a register. For information about addressing modes, see Load/Store addressing modes.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | imm19 | Rt | ||||||||||||||||||||||
| opc | VR | ||||||||||||||||||||||||||||||
constant integer t = UInt(Rt); constant boolean nontemporal = FALSE; constant boolean tagchecked = FALSE; constant bits(64) offset = SignExtend(imm19:'00', 64);
| <Xt> |
Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field. |
| <label> |
Is the program label from which the data is to be loaded. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4. |
constant bits(64) address = PC64 + offset; constant boolean privileged = PSTATE.EL != EL0; constant AccessDescriptor accdesc = CreateAccDescGPR(MemOp_LOAD, nontemporal, privileged, tagchecked); constant bits(32) data = Mem[address, 4, accdesc]; X[t, 64] = SignExtend(data, 64);
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: aarchmrs v2024-12_rel, pseudocode v2024-12_rel ; Build timestamp: 2024-12-15T22:18
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