Conditional Negate returns, in the destination register, the negated value of the source register if the condition is TRUE, and otherwise returns the value of the source register.
This is an alias of CSNEG. This means:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | Rm | != 111x | 0 | 1 | Rn | Rd | |||||||||||||||
| op | cond | o2 | |||||||||||||||||||||||||||||
is equivalent to
CSNEG <Wd>, <Wn>, <Wn>, invert(<cond>)
and is the preferred disassembly when Rn == Rm.
is equivalent to
CSNEG <Xd>, <Xn>, <Xn>, invert(<cond>)
and is the preferred disassembly when Rn == Rm.
| <Wd> |
Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. |
| <Wn> |
Is the 32-bit name of the general-purpose source register, encoded in the "Rn" and "Rm" fields. |
| <Xd> |
Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. |
| <Xn> |
Is the 64-bit name of the general-purpose source register, encoded in the "Rn" and "Rm" fields. |
| <cond> |
Is one of the standard conditions, excluding AL and NV, encoded in the "cond" field with its least significant bit inverted. |
The description of CSNEG gives the operational pseudocode for this instruction.
Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.