Atomic exclusive OR on word or doubleword in memory, without return, atomically loads a 32-bit word or 64-bit doubleword from memory, performs an exclusive OR with the value held in a register on it, and stores the result back to memory.
For information about memory accesses, see Load/Store addressing modes.
This is an alias of LDEOR, LDEORA, LDEORAL, LDEORL. This means:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | x | 1 | 1 | 1 | 0 | 0 | 0 | 0 | R | 1 | Rs | 0 | 0 | 1 | 0 | 0 | 0 | Rn | 1 | 1 | 1 | 1 | 1 | ||||||||
| size | A | opc | Rt | ||||||||||||||||||||||||||||
STEOR <Ws>, [<Xn|SP>] // (PSTATE.C64 == '0')
STEOR <Ws>, [<Cn|CSP>] // (PSTATE.C64 == '1')
is equivalent to
LDEOR <Ws>, WZR, <Addressing_Mode>
and is always the preferred disassembly.
STEORL <Ws>, [<Xn|SP>] // (PSTATE.C64 == '0')
STEORL <Ws>, [<Cn|CSP>] // (PSTATE.C64 == '1')
is equivalent to
LDEORL <Ws>, WZR, <Addressing_Mode>
and is always the preferred disassembly.
STEOR <Xs>, [<Xn|SP>] // (PSTATE.C64 == '0')
STEOR <Xs>, [<Cn|CSP>] // (PSTATE.C64 == '1')
is equivalent to
LDEOR <Xs>, XZR, <Addressing_Mode>
and is always the preferred disassembly.
STEORL <Xs>, [<Xn|SP>] // (PSTATE.C64 == '0')
STEORL <Xs>, [<Cn|CSP>] // (PSTATE.C64 == '1')
is equivalent to
LDEORL <Xs>, XZR, <Addressing_Mode>
and is always the preferred disassembly.
| <Ws> |
Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field. |
| <Xs> |
Is the 64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Cn|CSP> |
Is the name of the capability register or capability stack pointer holding the base address, encoded in the "Rn" field. |
The description of LDEOR, LDEORA, LDEORAL, LDEORL gives the operational pseudocode for this instruction.
Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23
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